Semiconductor device having various widths under gate

ABSTRACT

One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.

RELATED APPLICATION

This application claims priority to U.S. application Ser. No. 11/948,172filed Nov. 30, 2007, entitled “MATCHED ANALOG TRANSISTORS WITH EXTENSIONWELLS.”

FIELD OF INVENTION

The present invention relates generally to semiconductor devices andmore particularly to methods and systems for providing matchedtransistors.

BACKGROUND OF THE INVENTION

Since semiconductor transistors were first implemented, there has beenan on-going effort to reduce the area that individual transistors takeup on an integrated circuit (i.e., “shrink” them), thereby allowing moretransistors to fit on the integrated circuit. This trend is one factorthat helps manufacturers to produce more powerful integrated circuitsthat have more functionality than previous generations. Indeed, this isone factor that has helped to usher in the communication age as we knowit.

In addition to shrinking the area of individual transistors, in manyapplications designers also go to great lengths to match thecharacteristics of various transistors on a single integrated circuit.For example, designers often match transistors' geometries (i.e.,layouts) so that the transistors experience similar electrical stresseswith respect to surrounding devices. Depending on design constraints,designers may want to match the gains (β), currents delivered (I_(DS)),voltage thresholds (V_(T)), or other transistor characteristics of twoor more transistors.

Accordingly, there is an on-going need for integrated circuits thatstrike a balance between minimal transistor area and precise matching.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summarypresents one or more concepts of the invention in a simplified form as aprelude to the more detailed description that is presented later and isnot an extensive overview of the invention. In this regard, the summaryis not intended to identify key or critical elements of the invention,nor does the summary delineate the scope of the invention.

One embodiment of the invention relates to a semiconductor device formedover a semiconductor body. In this device, source and drain regions areformed in the body about lateral edges of a gate electrode and areseparated from one another by a gate length. A channel region, which isconfigured to allow charged carriers to selectively flow between thesource and drain regions during operation of the device, has differingwidths under the gate electrode. These widths are generallyperpendicular to the gate length. Other devices, methods, and systemsare also disclosed.

The following description and annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative of but a few of the various ways in which the principlesof the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C show a somewhat conventional transistor;

FIGS. 2A-2C show a top view and cross-sectional views of someillustrative I-shaped transistors;

FIG. 3 shows a top-view of a T-shaped transistor;

FIG. 4 shows a top-view of an array of T-shaped transistors;

FIG. 5A-5B shows additional embodiments of transistors in accordancewith aspects of the invention;

FIG. 6A-6B shows additional embodiments of transistors in accordancewith aspects of the invention;

FIG. 7 shows a method for manufacturing a transistor in accordance withaspects of the invention;

FIGS. 8-12 show a transistor at various stages of manufacture, inaccordance with one embodiment of the method shown in FIG. 7;

FIGS. 13-16 show graphical plots in accordance with aspects of oneembodiment of the invention; and

FIG. 17 shows a circuit having first and second matched transistors.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to theattached drawing figures, wherein like reference numerals are used torefer to like elements throughout, and wherein the illustratedstructures and devices are not necessarily drawn to scale.

Referring now to FIG. 1A-1C, one can see a somewhat traditionalmetal-oxide semiconductor field effect transistor 100 (MOSFET) that isformed over a semiconductor substrate 102. An isolation trench 104,which typically comprises oxide or another dielectric, surrounds arectangular isolated region 106 within the semiconductor body. In theillustrated embodiment, the isolated region 106 may correspond to alightly doped well 108, which is formed within the substrate 102. Often,one can think of the isolation trench 104 as a “sea” surrounding islandsof silicon where devices are built.

A gate-electrode 110, about which a source 112 and drain 114 arelaterally disposed, overlies the substrate 102. Pocket implant regions116, 118 can be formed near the lateral edges of the gate-electrode,where a bulk region 120 separates the pocket implants from one another.A dielectric layer 122 directly overlies the substrate 102, providingelectrical isolation between the gate electrode 110 and a channel regionin the body between the source 112 and drain 114.

Typically, the source and drain 112, 114 have a first conductivity type,while the bulk region 120 and pocket implant regions 116, 118 have asecond conductivity type that is opposite to the first conductivitytype. For example, in the illustrated embodiment, the source and drain112, 114 are p-type (highly doped P++), while the bulk region 120 andpocket implant regions 116, 118 are n-type (lightly doped N−, and highlydoped N+, respectively). In such a configuration (i.e., a PMOS device),the substrate could be lightly doped p-type material (P−). As shown inFIG. 1C, the device may also include source and drain extension regions.

During operation, current selectively flows between the source and drain112, 114 through the pocket implant regions 116, 118 and the bulk region120 (i.e., through the channel region), depending on the bias applied tothe device.

Referring now to FIG. 17, one can see an example of an integratedcircuit 1700 that includes first and second matched transistors 1702,1704 (e.g., metal-oxide-semiconductor field effect transistors(MOSFETs)), which have identical length-to-width ratios. The matchedtransistors 1702, 1704 are associated with analog circuitry thatutilizes a matching characteristic of the first and second matchedtransistors to facilitate analog functionality. In the illustratedembodiment, the first and second matched transistors 1702, 1704 comprisea current mirror where the first and second matched transistors 1702,1704 provide matched currents I_(Ref), I₀ along two legs of the currentmirror. Thus, because a common gate voltage is applied to the gateelectrodes of the matched transistors 1702, 1704 and a common (albeitchanging) drain-source voltage (V_(DS)) is also established, thetransistors could provide matched currents I_(Ref), I₀ between theirsources and drains (I_(DS)). This allows the current mirror to be usedto supply current to another block. In other embodiments, matchedtransistors could be used in amplifiers, or any number of other types ofanalog circuits.

As the inventors have appreciated, the previously discussed conventionalMOSFET transistor 100 is in some ways ill-suited for use in such ananalog circuit 1700. More specifically, the inventors have appreciatedthat the pocket implant regions 116, 118 often act as a “blockade” toregulate the amount of current that actually flows through the device.Because the concentration of dopant atoms in the pocket implant regions116, 118 is difficult to precisely control (e.g., due to statisticalvariations in the small number of atoms that make up the pocket region),the potential barriers associated with the pocket implant regions canvary widely from one transistor to another. This makes it difficult toprecisely match one transistor to another, particularly at low overdrive(V_(GS)−V_(T)) values used to save headroom in analog circuits.

By analyzing the relative contributions of the bulk region 120 andpocket regions 116, 118 to matching in the device 100, the inventorshave appreciated that the majority of the area in the bulk region 120may be wasted in terms of the ability to match one transistor toanother. The inventors have taken advantage of this realization byfashioning devices with “I-shaped” or “T-shaped” channel regions insteadof more typical rectangular-shaped channel regions. These I-shaped orT-shaped channel regions could be achieved by forming correspondinglyshaped isolation structures or by corresponding doping variations underthe gate electrode. Some illustrative devices and methods are now setforth below.

Referring now to FIG. 2A-2C, one can see a transistor 200 formed withinan I-shaped shallow trench isolation structure that facilitates anI-shaped channel region. Like transistor 100, transistor 200 is formedover a semiconductor substrate 202 in which a well 204 is formed.Transistor 200 also includes a gate electrode 206 having gate length, L,which separates a source 208 from a drain 210, and pocket implantregions 212, 214, which are separated from one another by a bulk region216. In some embodiments, the gate electrode may also include spacers orother un-illustrated features.

The transistor 200 is formed within an isolation trench 218 that definesan I-shaped isolated region 220 in the semiconductor body 102. Thisisolated region 220 includes the I-shaped bulk region 216 and the pocketimplant regions 212, 214, where different widths are associatedtherewith. One can see that the I-shaped bulk region 216, which may alsobe referred to as a first region in some embodiments, has various widthsw₁, w₂, w₃ under the gate 206. In the illustrated embodiment, width w₁is measured between a pair of opposing sidewalls 216A, 216B, w₂ ismeasured between opposing sidewalls 210A, 210B, and w₃ is measuredbetween opposing sidewalls 208A, 208B. All of these sidewalls areadjacent to the isolation trench 218.

Often, the pocket implant regions do not coincide precisely with therelatively wide regions of the I-shaped bulk region. Rather, therelatively wide regions typically extend further under the gate than thepocket implants to avoid current crowding.

In various embodiments where the device 200 is used in an analog manner,this width w₁ could typically be less than the gate length L. Forexample, width w₁ could be less than the gate length L by a factor ofapproximately 1 to approximately 50. The drain 210 and source 208, whichin some embodiments may be referred to as a second region and thirdregion, respectively, have a second width w₂ and a third width w₃respectively. In the I-beam configuration 200, the second and thirdwidths w₂, w₃ are approximately equal to one another and are greaterthan the first width w₁. However, in other embodiments (e.g., in aT-shaped configuration discussed below), these widths w₂, w₃ coulddiffer from one another.

In one embodiment, these widths w₁, w₂, w₃, can be tailored such thattwo matched transistors in separate isolation structures are optimallymatched to one another, while they also take up a minimal area on theintegrated circuit. In effect, this configuration allows a designer to“shrink” a rectangular-shaped device without sacrificing quality ofmatching. For example, in one embodiment, a designer may want thematching precision of a rectangular-shaped MOSFET having a length of 20um and a width of 2 um, but cannot tolerate the large area (i.e., atleast 20 um*2 um=40 um²) required for such a device. Thus, the designercould use an I-shaped MOSFET where the pocket regions have lengthsL₂=L₃=(about 0.5 um) and widths w₂=w₃=(about 2 um). The designer coulduse a bulk region with a total length (L−L₂−L₃)=(about 2 um) and a widthw₁=(about 0.5 um). Thus, the I-shaped device with similar matchingcharacteristics would have an active area of about (2×(2 um×0.5 um)+(0.2um*2 um)=2.4 um²), in other words consuming a rectangular area of (0.5um+2 um+0.5 um)*2 um=6 um². Thus, the I-shaped device results in asignificant reduction in area in comparison to a rectangular-shapeddevice. Of course, these values are only illustrative and it will beappreciated that the lengths and widths of transistors in accordancewith the invention could vary widely from those set forth here.

As shown in FIG. 2C, in various embodiments the transistor 200 may alsoinclude extension regions 222, 224 adjacently underlying the gateelectrode 206 and adjacent to the source 208 and drain 210,respectively. These extension regions 222, 224 typically have the sameconductivity type as the source and drain 208, 210, albeit at slightlylower concentrations. Thus, in the illustrated example, the source anddrain 208, 210 are doped P++, while the source/drain extension regions222, 224 are doped P+.

Referring now to FIG. 3, one can see another transistor 300 formedwithin a shallow trench isolation structure 302 that defines a T-shapedisolated region 304. As shown, in this embodiment, the isolated region304 may include a T-shaped bulk region 216 under the gate 206 with firstand second widths w₁, w₂. The drain 210 and pocket region 214 may sharethe second width w₂, while the source 208 and pocket region 212 mayshare the first width w₃=w₁. Notably, in some embodiments, thistransistor 300 may still have substantially the same matching ability astransistor 200, but consumes less area on the die.

The T-shaped transistors may be advantageous in that they can be tiledtogether in an inter-digitated configuration 400 as shown in FIG. 4. Byinter-digitating the T-shaped transistors in this configuration 400, adenser layout may be achieved, potentially providing greaterfunctionality for the overall integrated circuit. As illustrated, inthis configuration 400, a first transistor 402 is formed within anisolation structure 404 and has a wide drain 406 and a narrow source408. A second transistor 410 is formed such that is also has a widedrain 414 and narrow source 416. However, the second transistor 410 istranslated vertically by a distance H, relative to the first transistor402. The second transistor 410 is also flipped horizontally about acentral axis 418 relative to the first transistor 402. Additionaltransistors (e.g., transistors 420, 422, 424, 426) are also positionedin this manner. As shown, adjacent columns of transistors may be flippedabout another vertical axis 428 relative to one another.

FIGS. 5-6 show some additional embodiments that may employed incombination with those devices discussed above. Generally speaking, inthese illustrated embodiments, the corners in the I-shaped or T-shapedlayouts are limited to minimize process-related mechanical stresses orlithography sensitivity. For example, tapered or rounded corners couldminimize current crowding. As shown in FIG. 5A, an I-shaped layout 500may have tapered regions 502, 504 under the gate 206. As shown, in FIG.5B, a T-shaped layout 506 may also have a tapered region 508.

As shown in FIG. 6A, an I-shaped layout 600 could also include roundedcorners 602, 604. In various embodiments, these rounded corners 602, 604could follow a Fermi-function shape. As shown in FIG. 6B, a T-shapedlayout 606 could similarly use rounded corners or a Fermi-functionshape.

Referring now to FIGS. 7-12, one can see same examples of methods formaking the structures described above. FIG. 7 shows a flowchartillustrating a somewhat general method, while FIGS. 8-12 show examplesof various structures that could correspond to the blocks of theflowchart. Although this method is illustrated and described below as aseries of acts or events, it will be appreciated that the presentinvention is not limited by the illustrated ordering of such acts orevents. For example, some acts may occur in different orders and/orconcurrently with other acts or events apart from those illustratedand/or described herein, in accordance with the invention. In addition,not all illustrated steps may be required to implement a methodology inaccordance with the present invention. Furthermore, the methodsaccording to the present invention may be implemented in associationwith the devices and systems illustrated and described herein as well asin association with other structures not illustrated.

Referring now to FIG. 7, one can see method 700 starts at block 702 withan un-patterned semiconductor body. In block 704, a shallow trenchisolation structure is formed in the semiconductor body to isolateindividual devices or groups of devices. In block 706, a well implant isperformed. In block 708, a polysilicon gate is formed over thestructure. In block 710, implants are performed to form the source/drainregions and the pocket implant regions.

In FIG. 8, one can see a semiconductor substrate 202, which couldcomprise a Si, GaAs, SiGe, Silicon-on-insulator, or any othersemiconductor substrate.

In FIG. 9A-9B, one can see an isolation structure 218 that is formedwithin the semiconductor body. In FIG. 9A's illustrated embodiment, onecan see a top-level view of an I-shaped isolated region 208. FIG. 9Bshows a cross sectional view along the cut-away line shown in FIG. 9A.

In FIG. 10A-10B, an ion implant is performed to form a well 204 withinthe semiconductor substrate. In an embodiment where the substrate isp-type, an n-well could be used to isolate PMOS devices and a p-wellcould be implanted within the substrate to provide the body for NMOSdevices.

In FIGS. 11A-11B (which show a top-view and cross-sectional view,respectively), show a gate structure 206 formed over the semiconductorbody. In various embodiments, this gate structure could comprisepolysilicon or metal.

In FIGS. 12A-12B show the device after a source/drain implant has beenused to form a source region 208 and a drain region 210. An angledpocket implant has also been used to form pocket implant regions 212,214. In addition, another implant has been used to form source-drainextension regions 222, 224, which could use the same mask as the pocketimplant.

Referring now to FIG. 13-16, one can see some graphs that show someperformance characteristics of one embodiment of an I-beam devicecompared to that of a rectangular device. The graphs are in a standardformat for matching studies and were performed using a thin gate oxideNMOS device in a 65 nm technology. In these graphs the horizontal axisis (1/√{square root over (TransistorActiveArea)}), and the vertical axisis the standard deviation of the mismatch parameter of interest.Generally speaking, the “best” place to be on each graph is at the lowerright-hand corner, where the area is small (compact layout) and thematching is tight (low sigma mismatch distribution).

The layout dimensions of studied in FIGS. 13-16 were as follows. Therectangular devices had (W/L) values of (2/20), (1/10), (0.5, 5), and(0.2/2). By virtue of its large active area, the (W/L)=(2/20)rectangular device corresponds to the data point at the lower left-handcorner of each graph. The I-beam devices were laid out with W₂=W₃=2 um,with varying (W₁/L₁) values of (1/10), (0.5/5), and (0.2/2). The(W₁/L₁)=(1/10) corresponds to the left-most data point in the graphssince it has the largest active area of any of the I-beam devices. Sinceall of the I-beam devices had pocket regions with a width of 2 um, theI-beam devices are expected to show matching similar to that of therectangular (2/20) device, if in fact the width of the pocket regiondoes dominate transistor matching.

Four mismatch parameters were analyzed for each device style. Moreprecisely, FIG. 13 shows the voltage threshold (V_(T)) mismatch; FIG. 14shows the beta mismatch; FIG. 15 shows the current mismatch forsub-threshold inversion (where V_(GS)−V_(T) is approximately equal to 0mV); and FIG. 16 shows the current mismatch for strong inversion (whereV_(GS)−V_(T) is approximately equal to 200 mV). For all cases,V_(DS)=V_(DD), so the measurements were in the saturation regime. Asshown in FIG. 13-16, the I-beam structures have more compact layout thanthe (W/L)=(2/20) rectangular device, but they produce similar values ofmatching, thus showing that the matching of these long-channel devicesis largely dominated by the width of the pocket implant regions ratherthan the area of the bulk region.

Although matched transistors (e.g., transistors 200, 300) and methodsfor performing operations thereon have been illustrated and described,alterations and/or modifications may be made to these examples. Forexample, although transistor 200 has been shown as having an n-type bulkregion, a p-type source, and a p-type drain (i.e., a PMOS device); inother embodiments the doping conventions could be reversed. For example,the bulk region could be p-type, and the source and drain could ben-type (i.e., an NMOS device). Alternatively, the present inventioncould be used with an NMOS device that is placed with a p-well or ashallow p-well as the body, such that the body is contained within adeep n-well, isolating the body from a p-type substrate.

Although as described herein, the terms “first region” and “first width”were used to describe a bulk region in one embodiment, these terms alsoinclude other structures. For example, these terms could also relate tothe source, drain, or pocket implant regions, or they could relate toother structures in other devices (e.g., bipolar transistors).Similarly, the terms “second region”, “second width”, “third region”,“third width”, “fourth region”, “fourth width”, and other related termscould include any other structures and should not be limited to thosestructures described above. In various embodiments, these regions couldbe defined without using a shallow trench isolation structure. Forexample, the first and second regions could be achieved by dopingvariations or other manners of differentiating between regions.

Although the invention has been illustrated and described with respectto one or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and the claims, such termsare intended to be inclusive in a manner similar to the term“comprising”.

1. A semiconductor device formed over a semiconductor body, comprising:source and drain regions formed in the body about lateral edges of agate electrode and separated from one another by a gate length; and achannel region configured to allow charged carriers to selectively flowbetween the source and drain regions during operation of the device, thechannel region having different widths under the gate electrode, whichwidths are generally perpendicular to the gate length.
 2. The device ofclaim 1, where an isolation trench defines the widths of the channelregion under the gate.
 3. The device of claim 1, where channel regionhas at least one, if not all, of the following three curvatures:tapered, rounded, and fermi function.
 4. The device of claim 1, wherethe channel region comprises a bulk region having a first width; andwhere the drain region has a second width that is greater than the firstwidth.
 5. The device of claim 4, where the channel region furthercomprises: a pocket implant region laterally disposed between the drainregion and the bulk region and having a third width that is greater thanthe first width.
 6. The device of claim 5, where the first and thirdwidths vary from one another as a function of an extent to which thebulk region and pocket implant region can provide matched electricalcharacteristics.
 7. An isolated region of a semiconductor bodysurrounded by an isolation trench, the isolated region comprising: afirst region of the semiconductor body comprising a first set ofopposing sidewalls that are adjacent to the isolation trench andseparated from one another by a first width, the first region having afirst doping conductivity; and a second region of the semiconductor bodycomprising a second set of opposing sidewalls that are adjacent to theisolation trench and separated from one another by a second width thatis greater than the first width, the second region having a seconddoping conductivity that is opposite the first doping conductivity. 8.The isolated region of claim 7, further comprising: a pocket implantregion between the first region and the second region, the pocketimplant region comprising opposing sidewalls that are separated from oneanother by approximately the second width and having the first dopingconductivity.
 9. The isolated region of claim 7, further comprising: athird region comprising a third set of opposing sidewalls that areadjacent to the isolation trench and separated from one another by athird width, the third region having the second doping conductivity. 10.The isolated region of claim 9, where the third width is approximatelyequal to the first width.
 11. The isolated region of claim 9, where thethird width is approximately equal to the second width.
 12. The isolatedregion of claim 9, where the third width is greater than the first widthand less than the second width.
 13. An integrated circuit formed over asemiconductor body, comprising: a semiconductor device that comprises: agate electrode formed over the semiconductor body; a source region and adrain region formed in the body and disposed about opposing lateraledges of the gate electrode; an isolation trench that surrounds anisolated region of the semiconductor body, which isolated regioncomprises: a first set of opposing sidewalls separated by a first widthunder the gate electrode, and a second set of opposing sidewallsseparated by a second width under the gate electrode, the second widthbeing greater than the first width.
 14. The integrated circuit of claim13, where the isolated region further comprises: a third set of opposingsidewalls associated with the drain region and separated byapproximately the second width.
 15. The integrated circuit of claim 14,where the isolated region further comprises: a fourth set of opposingsidewalls associated with the source region and separated by a fourthwidth that is approximately equal to the first width.
 16. The integratedcircuit of claim 13, where the isolated region further comprises: pocketimplant regions formed in the semiconductor body near the opposinglateral edges of the gate electrode.
 17. The integrated circuit of claim16, where at least one of the pocket implant regions has approximatelythe second width.
 18. The integrated circuit of claim 13, furthercomprising: a second semiconductor device that comprises: another gateelectrode formed over the semiconductor body; another source region andanother drain region formed in the body and disposed about opposinglateral edges of the another gate electrode; another isolated region ofthe semiconductor body, which another isolated region has a geometrythat matches that of the isolated region.
 19. The integrated circuit ofclaim 18, where the isolated region and the another isolated region haveat least one, if not all, of the following two geometries: i-shaped andt-shaped.
 20. An integrated circuit, comprising: a first matchedtransistor, comprising: first source and drain regions formed aboutlateral edges of a first gate electrode, the first source and drainregions separated from one another by a first channel region havingdifferent widths under the first gate electrode; a second matchedtransistor, comprising: second source and drain regions formed aboutlateral edges of a second gate electrode, the second source and drainregions separated from one another by a second channel region havingdifferent widths under the second gate electrode; and analog circuitryassociated with the first and second matched transistors, which analogcircuitry utilizes a matching characteristic of the first and secondmatched transistors to facilitate analog functionality.